R5F72115D160FPV datasheet(1114/1228 Pages) RENESAS

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Section 27 Electrical Characteristics

Rev. 2.00 May. 08, 2008 Page 1090 of 1200

REJ09B0344-0200

27.4.1

Clock Timing

Table 27.6

Clock Timing

Conditions: Vcc = PLLVcc = 1.4 to 1.6 V, VccQ = 3.0 to 3.6 V,

Vss = PLLVss = VssQ = 0 V, Ta =

−40°C to +85°C

Item

Symbol Min.

Max.

Unit

Figure

EXTAL clock input frequency

MHz

EXTAL clock input cycle time

EXcyc

100

125

EXTAL clock input pulse low width

EXL

–

EXTAL clock input pulse high width

EXH

–

EXTAL clock input rise time

EXr

–

EXTAL clock input fall time

EXf

–

Figure 27.3

CK clock output frequency

MHz

CK clock output cycle time

cyc

25.0

62.5

CK clock output pulse low width

CKOL

–

CK clock output pulse high width

CKOH

–

CK clock output rise time

CKOr

–

CK clock output fall time

CKOf

–

Figure 27.4

Power-on oscillation setting time

OSC1

–

Figure 27.5

Oscillation settling time on return from

standby 1

OSC2

–

Figure 27.6

Oscillation settling time on return from

standby 2

OSC3

–

Figure 27.7

EXH

EXf

tEXr

EXL

EXcyc

VIH

1/2 VccQ

VIL

EXTAL*

(input)

Note: * When the clock is input on the EXTAL pin.

Figure 27.3 EXTAL Clock Input Timing

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