R5F72115D160FPV datasheet(1117/1228 Pages) RENESAS

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Section 27 Electrical Characteristics

Rev. 2.00 May. 08, 2008 Page 1093 of 1200

REJ09B0344-0200

27.4.2

Control Signal Timing

Table 27.7

Control Signal Timing

Conditions: Vcc = PLLVcc = 1.4 to 1.6 V, VccQ = 3.0 to 3.6,

Vss = PLLVss = VssQ = 0 V, Ta =

−40°C to +85°C

φ = 40 MHz

Item

Symbol Min.

Max.

Unit

Figure

RES pulse width

RESW

20*

–

cyc

RES setup time *1

RESS

–

RES hold time

RESH

–

MRES pulse width

MRESW

20*

—

cyc

MRES setup time

MRESS

–

MRES hold time

MRESH

–

Figure 27.5,

Figure 27.6,

Figure 27.8,

Figure 27.9

MD1, MD0 setup time

MDS

–

cyc

Figure 27.8

BREQ setup time

BREQS

1/2t

cyc + 10

–

Figure 27.10

BREQ hold time

BREQH

1/2t

cyc + 4

–

NMI setup time *

NMIS

–

Figure 27.9

NMI hold time

NMIH

–

IRQ7 to IRQ0 setup time *

IRQS

–

IRQ7 to IRQ0 hold time

IRQH

–

IRQOUT/REFOUT output delay time

IRQOD

—

100

Figure 27.11

BACK delay time

BACKD

—

1/2t

cyc + 20

Bus tri-state delay time 1

BOFF1

100

Bus tri-state delay time 2

BOFF2

100

Bus buffer on time 1

BON1

Figure 27.10

Bus buffer on time 2

BON2

Notes: 1.

RES, NMI, and IRQ7 to IRQ0 are asynchronous signals. When these setup times are

observed, a change of these signals is detected at the clock rising edge. If the setup

times are not observed, detection of a signal change may be delayed until the next

rising edge of the clock.

2. In standby mode or when the clock multiplication ratio is changed, t

RESW = tOSC2 (Min. 10

ms).

3. In standby mode, t

RESW = tOSC2 (Min. 10 ms).

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