bq78PL114

TERMINAL FUNCTIONS (continued)

NAME

NO.

DESCRIPTION

P1N

15

O

Charge-balance gate drive, cell 1 north

P2S

16

O

Charge-balance gate drive, cell 2 south

P2N

17

O

Charge-balance gate drive, cell 2 north

P3N

21

O

Charge-balance gate drive, cell 3 north

P3S

20

O

Charge-balance gate drive, cell 3 south

P4N

23

O

Charge-balance gate drive, cell 4 north

P4S

22

O

Charge-balance gate drive, cell 4 south

P-LAN

24

IO

PowerLAN I/O to external bq76PL10x nodes

PRE

3

O

Pre-Charge MOSFET control (active-high.)

RSTN

25

I

Device reset, active-low

SDI1

14

I

Connect to SDO0 via a capacitor

SDI3

19

I

Internal PowerLAN connection – connect to SDO2

SDO0

13

O

Requires 100-k

Ω pullup resistor to VLDO1

SDO2

18

O

Internal PowerLAN connection – connect to SDI3

SELECT

29

O

SMBCLK

37

IO

SMBus clock signal

SMBDAT

38

IO

SMBus data signal

SPI-CLK

26

IO

SPI-DI

27

I

SPI-DO

28

O

SPROT

30

O

Secondary protection output, active-high (FUSE)

V1

47

IA

Cell-1 positive input

V2

44

IA

Cell-2 positive input

V3

42

IA

Cell-3 positive input

V4

39

IA

Cell-4 positive input

VLDO1

8

P

Internal LDO-1 output, bypass with capacitor

VLDO2

43

P

Internal LDO-2 output, bypass with capacitor

VSS

48

IA

Cell-1 negative input

XT1

46

IA

External temperature-sensor-1 input

XT2

45

IA

External temperature-sensor-2 input

XT3

41

IA

External temperature-sensor-3 input

XT4

40

IA

External temperature-sensor-4 input

–

–

P

Thermal pad. Connect to VSS

(2)

SPI functionality requires a firmware option, consult the factory for additional information.

Copyright © 2008, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): bq78PL114