M32CSLASH8A datasheet(361/372 Pages) RENESAS

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M32C/8A Group

24. Usage Notes

Rev.1.00

Jul 15, 2007

Page 344 of 352

REJ09B0385-0100

24.7.3

Timer B

24.7.3.1

Timer B (Timer Mode, Event Counter Mode)

• The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 0 (count stops) after reset. Set the TBiS

bit to 1 (count starts) after selecting timer operating mode and setting the TBi register.

Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR

• The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read

in the reload timing. A setting value can be read between setting the TBi register while a counter stops and

starting a counter.

24.7.3.2

Timer B (Pulse Period/Pulse Width Measurement Mode)

• To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR

(Technical update: TN-M16C-75-0110)

• Use the IR bit in the TBiIC register to detect overflow. The MR3 bit is used only to determine an interrupt

request source within the interrupt routine.

• When the first valid edge is input after the count starts, an undefined value is transferred to the reload

• The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and

causes a timer Bi interrupt request to be generated before a valid edge is input.

• The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after

the count starts. If the same value is written to bits MR1 and MR0, the IR bit is not changed.

• Pulse width is repeatedly measured in pulse width measurement mode. Determine by program whether the

measurement result is high (“H”) or low (“L”).

• If an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt

request is generated only once, which results in the valid edge not being recognized. Do not let an overflow

occur.

• In pulse width measurement mode, determine whether an interrupt source is a valid edge input or an

overflow by reading the port level in the TBi interrupt routine.

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