M32CSLASH8A datasheet(363/372 Pages) RENESAS

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M32C/8A Group

24. Usage Notes

Rev.1.00

Jul 15, 2007

Page 346 of 352

REJ09B0385-0100

24.9

Serial Interfaces

24.9.1

Changing UiBRG Register (i = 0 to 4)

Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are

changed, the UiBRG register must be set again.

24.9.2

Clock Synchronous Mode

24.9.2.1

Transmit Operation

If an external clock is selected, the following conditions must be met while the external clock is held “H” when

the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive

data input at the rising edge of the serial clock), or while the external clock is held “L” when the CKPOL bit is

set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)

• Set the TE bit in the UiC1 register to 1 (transmit operation enabled).

• Set the RE bit in the UiC1 register to 1 (receive operation enabled).

• The TI bit in the UiC1 register is 0 (data in the UiTB register).

The RE bit setting is not required for a transmit-only operation.

24.9.2.2

Receive Operation

• In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTi-

associated registers for a transmit operation as well, even if the MCU is used only for receive operation.

Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.

• If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the

UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the

OER bit in the UiRB register becomes 1 (overrun error occurred). In this case, the UiRB register becomes

undefined. If an overrun error occurs, the IR bit in the SiRIC register is not changed to 1.

• The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).

(1) The CKDIR bit in the UiMR register is set to 1 (external clock).

(2) The RTS function is not used.

To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode

disabled), and write dummy data to the UiTB register every time a receive operation is completed.

24.9.3

UART Mode

Set the UiERE bit in the UiC1 register after setting the UiMR register.

24.9.4

Special Mode 1 (I2C Mode)

To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the UiSMR4 register

to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit

(the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1.

(Technical update: TN-16C-130A/EA)

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