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H838532H Datasheet(PDF) 319 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 319 Page - Renesas Technology Corp |
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319 / 508 page ![]() Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 299 of 484 REJ09B0436-0100 Bit 7: Transmit data register empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7 TDRE Description 0 Transmit data written in TDR has not been transferred to TSR Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction 1 Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR Setting conditions: When bit TE in SCR3 is cleared to 0 When data is transferred from TDR to TSR (initial value) |
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