H838532H datasheet(322/508 Pages) RENESAS

322 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 302 of 484

REJ09B0436-0100

Bit 3: Parity error (PER)

Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous

mode.

Bit 3

PER

Description

Reception in progress or completed*

(initial value)

Clearing condition:

After reading PER = 1, cleared by writing 0 to PER

A parity error has occurred during reception*

Setting condition:

When the number of 1 bits in the receive data plus parity bit does not match the parity

designated by bit PM in the serial mode register (SMR)

Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous

state.

2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit

RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous

mode, neither transmission nor reception is possible when bit FER is set to 1.

Bit 2: Transmit end (TEND)

Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.

Bit 2 is a read-only bit and cannot be modified.

Bit 2

TEND

Description

Transmission in progress

Clearing conditions:

After reading TDRE = 1, cleared by writing 0 to TDRE

When data is written to TDR by an instruction

Transmission ended

(initial value)

Setting conditions:

When bit TE in SCR3 is cleared to 0

When bit TDRE is set to 1 when the last bit of a transmit character is sent

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