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H838532H Datasheet(PDF) 326 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 326 Page - Renesas Technology Corp |
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326 / 508 page ![]() Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 306 of 484 REJ09B0436-0100 Table 10.4 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φ w/2 *1/ φ w *2 0 1 2 φ/16 1 0 3 φ/64 1 1 Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only. Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active (high- speed) mode. Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting OSC (MHz) Maximum Bit Rate (bit/s) n N 0.0384* 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 *: When SMR is set up to CKS1 = “0”, CKS0 = “1”. Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. |
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