H8S2245 datasheet(601/818 Pages) RENESAS

601 / 818 page

Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 559 of 772

REJ09B0355-0300

Bit 7—

φφφφ Clock Output Disable (PSTOP): Controls φ output.

Description

Bit 7

PSTOP

Normal Operating

Mode

Sleep Mode

Software Standby

Mode

Hardware Standby

Mode

φ output (initial value)

φ output

Fixed high

High impedance

Fixed high

High impedance

Bits 6—Reserved: This bit can be read or written to, but only 0 should be written.

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus

master.

Bit 2

Bit 1

Bit 0

SCK2

SCK1

SCK0

Description

Bus master in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

——

18.2.3

Module Stop Control Register (MSTPCR)

R/W

Bit

Initial value

R/W

MSTPCRH

MSTPCRL

MSTPCR is a 16-bit readable/writable register that performs module stop mode control.

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