HD6432351 datasheet(657/1025 Pages) RENESAS

657 / 1025 page

Section 14 Smart Card Interface

Rev. 3.00 Sep 15, 2006 page 623 of 988

REJ09B0330-0300

[4] The receiving station carries out a parity check.

If there is no parity error and the data is received normally, the receiving station waits for

reception of the next data.

If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)

to request retransmission of the data. After outputting the error signal for the prescribed length

of time, the receiving station places the signal line in the high-impedance state again. The

signal line is pulled high again by a pull-up resistor.

[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data

frame.

If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous

data.

14.3.4

Table 14.3 shows a bit map of the registers used by the smart card interface.

Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described

below.

Table 14.3 Smart Card Interface Register Settings

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMR

CKS1

CKS0

BRR

BRR7

BRR6

BRR5

BRR4

BRR3

BRR2

BRR1

BRR0

SCR

TIE

RIE

CKE1*

CKE0

TDR

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1

TDR0

SSR

TDRE

RDRF

ORER

ERS

PER

TEND

RDR

RDR7

RDR6

RDR5

RDR4

RDR3

RDR2

RDR1

RDR0

SCMR

—

SDIR

SINV

—

SMIF

Notes: —: Unused bit.

*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.

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