HD6432351 datasheet(728/1025 Pages) RENESAS

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Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 694 of 988

REJ09B0330-0300

20.5.2

Usage Notes

DMAC/DTC Module Stop

Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not

be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the

respective module is not activated.

For details, refer to section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller

(DTC).

On-Chip Supporting Module Interrupt

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module

stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU

interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled

before entering module stop mode.

Writing to MSTPCR

MSTPCR should only be written to by the CPU.

20.6

Software Standby Mode

20.6.1

Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby

mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.

However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip

supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the

address bus and bus control signals are placed in the high-impedance state or retain the output

state can be specified by the OPE bit in SBYCR.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

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