HD6432351 datasheet(729/1025 Pages) RENESAS

729 / 1025 page

Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 695 of 988

REJ09B0330-0300

20.6.2

Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins

IRQ0 to IRQ2), or by

means of the

RES pin or STBY pin.

Clearing with an Interrupt

When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after

the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire

H8S/2350 Group chip, software standby mode is cleared, and interrupt exception handling is

started.

When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is

generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU

side or has been designated as a DTC activation source.

Clearing with the

RES

RES Pin

When the

RES pin is driven low, clock oscillation is started. At the same time as clock oscillation

starts, clocks are supplied to the entire H8S/2350 Group chip. Note that the

RES pin must be held

low until clock oscillation stabilizes. When the

RES pin goes high, the CPU begins reset exception

handling.

Clearing with the

STBY

STBY Pin

When the

STBY pin is driven low, a transition is made to hardware standby mode.

HD6432351 Datasheet(PDF) 729 Page - Renesas Technology Corp