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HD6432351 Datasheet(PDF) 732 Page - Renesas Technology Corp

Part # HD6432351
Description  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datasheet(HTML) 732 Page - Renesas Technology Corp

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Section 20 Power-Down Modes
Rev. 3.00 Sep 15, 2006 page 698 of 988
REJ09B0330-0300
20.6.5
Usage Notes
I/O Port Status
In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus
and bus control signal output is also retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
Current Dissipation during Oscillation Stabilization Wait Period
Current dissipation increases during the oscillation stabilization wait period.
Write Data Buffer Function
The write data buffer function and software standby mode cannot be used at the same time. When
the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the
write data buffer function before entering software standby mode. Also check that external writes
have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter
software standby mode. See section 6.9, Write Data Buffer Function, for details of the write data
buffer function.
20.7
Hardware Standby Mode
20.7.1
Hardware Standby Mode
When the
STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the
STBY pin low.
Do not change the state of the mode pins (MD2 to MD0) while the H8S/2350 Group is in hardware
standby mode.
Hardware standby mode is cleared by means of the
STBY pin and the RES pin. When the STBY
pin is driven high while the
RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the
RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the



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