HD64F2149YV datasheet(583/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 555 of 1044

REJ09B0280-0300

check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been

set.

• Notes on Interrupt Occurrence after ACKB Reception

 Conditions to cause this failure

The IRIC flag is set to 1 when both of the following conditions are satisfied.

• 1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set

to 1

• Rising edge of the 9th transmit/receive clock is input to the SCL pin

When the above two conditions are satisfied in slave receive mode, an unnecessary

interrupt occurs.

Figure 16.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the

acknowledge bit (ACKB = 1).

(1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received

as the acknowledge bit.

If the ACKE bit in ICCR is set to 1 at this time, the ACKB bit in ICSR is set to 1.

(2) After switching to slave receive mode, the start condition is input, and address

reception is performed next.

(3) Even if the received address does not match the address set in SAR or SARX, the IRIC

flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to

occur.

Note that if the slave address matches, an interrupt is to be generated at the rise of the 9th

transmit/receive clock as normal operation, so this is not erroneous operation.

 Restriction

In a transmit operation of the I

2C bus interface module, carry out the following

countermeasures.

(1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in

ICCR to 0 to clear the ACKB bit to 0.

(2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again.

HD64F2149YV Datasheet(PDF) 583 Page - Renesas Technology Corp