HD64F2149YV datasheet(581/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 553 of 1044

REJ09B0280-0300

• Notes on TRS Bit Setting in Slave Mode

From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the

rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23)

in the slave mode of the I

2C bus interface, the value set in the TRS bit in the ICCR register is

effective immediately.

However, at other times (indicated as (b) in figure 16.23) the value set in the TRS bit is put on

hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than

taking effect immediately.

This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no

acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an

address receive operation following a restart condition input with no stop condition

intervening.

When receiving an address in the slave mode, clear the TRS bit to 0 during the period

indicated as (a) in figure 16.23.

To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS

bit to 0 and then perform a dummy read of the ICDR register.

(a)

Restart condition

ICDR dummy read

Detection of 9th clock

cycle rising edge

TRS bit set

Detection of 9th clock

cycle rising edge

(b)

Data transmission

SDA

SCL

TRS

345

Address reception

TRS bit setting hold time

Figure 16.23 TRS Bit Setting Timing in Slave Mode

HD64F2149YV Datasheet(PDF) 581 Page - Renesas Technology Corp