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H8S2153 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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H8S2153 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 750 page  Section 1 Overview Rev. 2.00 Sep.11, 2008 Page 3 of 710 REJ09B0384-0200 1.2 Internal Block Diagram EVC AVCC AVref AVSS H8S/2600 CPU DTC RAM PE7/SERIRQ PE6/LCLK PE5/ LRESET PE4/ LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 PC7/PWX3 PC6/PWX2 PC3/SDA3 PC2/SCL3 PC1/SDA2 PC0/SCL2 PA7/EVENT7 PA6/EVENT6 PA5/EVENT5 PA4/EVENT4 PA3/EVENT3 PA2/EVENT2 PA1/EVENT1 PA0/EVENT0 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P37/ExDB7 P36/ExDB6 P35/ExDB5 P34/ExDB4 P33/ExDB3 P32/ExDB2 P31/ExDB1 P30/ExDB0 P47/ IRQ7/RS7/DB7/HC7 P46/ IRQ6/RS6/DB6/HC6 P45/ IRQ5/RS5/DB5/HC5 P44/ IRQ4/RS4/DB4/HC4 P43/ IRQ3/RS3/HC3 P42/ IRQ2/RS2/HC2 P41/ IRQ1/RS1/HC1 P40/ IRQ0/RS0/HC0 LPC XTAL EXTAL MD2 MD1 RES RESO STBY FWE NMI ETRST ETMS ETDO ETDI ETCK JTAG SCI ROM (Flash memory) Interrupt controller 16-bit FRT IIC × 4 channels 14-bit PWM × 4 channels WDT × 2 channels 8-bit timer × 4 channels CRC operation circuit 10-bit A/D Port 5 Port 6 Port 7 Port 8 Bus controller Figure 1.1 Internal Block Diagram |
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