H8S2153 datasheet(49/750 Pages) RENESAS

49 / 750 page

Section 2 CPU

Rev. 2.00 Sep.11, 2008 Page 13 of 710

REJ09B0384-0200

Section 2 CPU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending

on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1

Features

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H CPUs object programs

• General-register architecture

 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-nine basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data:

16 Mbytes

• High-speed operation

 All frequently-used instructions execute in one or two states

 8/16/32-bit register-register add/subtract: 1 state

 8 × 8-bit register-register multiply: 2 states

H8S2153 Datasheet(PDF) 49 Page - Renesas Technology Corp