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M16C80 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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M16C80 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 358 page ![]() 9 2 3 f o 5 0 0 2 , 2 0 . g u A 0 0 . 1 . v e R 0 0 1 0 - 7 8 1 0 B 9 0 J E R Page 28 6. Processor Mode p u o r G 0 8 / C 6 1 M Figure 6.2 Processor mode register 1 Processor mode register 1 (Note 1) :Flash memory version Symbol Address When reset PM1 000516 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Note 5: Rewrite this bit when the main clock is in division by 8 mode. ALE pin select bit (Note 3) 0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA b5 b4 PM15 PM14 Reserved bit Must always be set to “0” W R Reserved bit Must always be set to “1” (Note 5) 0 PM12 Internal memory wait bit 0 : No wait state 1 : Wait state inserted External memory area mode bit (Note 3) 0 0 : Mode 0 (P44 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) b1 b0 PM11 PM10 Processor mode register 1 (Note 1) :Mask ROM version ROMless version (144-pin version) Symbol Address When reset PM1 000516 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". ALE pin select bit (Note 3) 0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA b5 b4 PM15 PM14 Reserved bit Must always be set to “0” W R Nothing is assinged. When read, the content is indeterminate. 0 PM12 Internal memory wait bit 0 : No wait state 1 : Wait state inserted External memory area mode bit (Note 3) 0 0 : Mode 0 (P44 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) b1 b0 PM11 PM10 |
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