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M16C80 Datasheet(PDF) 73 Page - Renesas Technology Corp |
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M16C80 Datasheet(HTML) 73 Page - Renesas Technology Corp |
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73 / 358 page  9 2 3 f o 5 0 0 2 , 2 0 . g u A 0 0 . 1 . v e R 0 0 1 0 - 7 8 1 0 B 9 0 J E R Page 62 9. Interrupt Outline p u o r G 0 8 / C 6 1 M 9.6 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Figure 9.3 shows the interrupt control registers. When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits 2, 1, and 0 at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). Figure 9.4 shows the exit priority register. |
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