M32CSLASH86 datasheet(486/505 Pages) RENESAS

486 / 505 page

Page 463

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27.8 DMAC

• Set DMAC-associated registers while the MDi1 and MDi0 bits (i=0 to 3) in the channel to be used are set

to "002" (DMA disabled). Set the MDi1 and MDi0 bits to "012" (single transfer) or "112" (repeat transfer)

at the end of setup procedure to start DMA requests.

• Do not set the DRQ bit in the DMiSL register to "0" (no request).

If a DMA request is generated but the receiving channel is not ready to receive(1), the DMA transfer does

not occur and the DRQ bit is set to "0".

NOTES:

1. The MDi1 and MDi0 bits are set to "002" or the DCTi register is set to "000016" (transferred 0

times).

• To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1"

simultaneously.

e.g.,

OR.B #0A0h,DMiSL

; Set the DSR and DRQ bits to "1" simultaneously

• Do not generate a channel i DMA request when setting the MDi1 and MDi0 bits in the DMDj register

(j=0,1) corresponding to channel i to "012" (single transfer) or "112" (repeat transfer), if the DCTi register

of channel i is set to "1".

• Select the peripheral function which causes the DMA request after setting the DMA-associated regis-

______

ters. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write

"1" to the DCTi register.

• Enable DMA(2) after setting the DMiSL register (i=0 to 3) and waiting six BCLK cycles or more by

program.

NOTES:

2. DMA is enabled when the values set in the MDi1 and MDi0 bits in the DMDj register are

changed from "002" (DMA disabled) to "012" (single transfer) or "112" (repeat transfer).

27. Precautions (DMAC)

M32C/86 Datasheet(PDF) 486 Page - Renesas Technology Corp