M32CSLASH86 datasheet(490/505 Pages) RENESAS

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27.10 Serial I/O

27.10.1 Clock Synchronous Serial I/O Mode

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The RTS2 and CLK2 pins are placed in high-impedance states when a low-level ("L") signal is applied to

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the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three-

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phase output by an "L" signal applied to the NMI pin).

27.10.1.1 Transmission /Reception

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When the RTS function is used while an external clock is selected, the output level of the RTSi pin is

held "L" indicating that the microcomputer is ready for reception. The transmitting microcomputer is

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notified that reception is possible. The output level of the RTSi pin becomes high ("H") when reception

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begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer synchro-

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nizes transmission and reception. The RTS function is disabled if an internal clock is selected.

27.10.1.2 Transmission

When an external clock is selected while the CKPOL bit in the UiC0 (i=0 to 4) register is set to "0" (data

is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external

clock is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the

transfer clock and received on the falling edge) and the external clock is held "L", meet the following

conditions:

• Set the TE bit in the UiC1 register to "1" (receive enabled)

• Set the TI bit in the UiC1 register to "0" (data in the UiTB register)

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• Apply "L" signal to the CTSi pin if the CTS function is selected

27.10.1.3 Reception

Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore,

set for transmission even if the microcomputer is used for reception only. Dummy data is output from

the TxDi pin while receiving.

If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1 registers is set

to "1" (receive enabled) and dummy data is set in the UiTB register. If an external clock is selected, the

shift clock is generated when the external clock is input into CLKi pin while the TE bit is set to "1"

(receive enabled) and dummy data is set in the UiTB register.

When receiving data consecutively while the RE bit in the UiC1 register is set to "1" (data in the UiRB

the OER bit in the UiRB register is set to "1" (overrun error). In this case, the UiRB register is indeter-

minate. When overrun error occurs, program both reception and transmission registers to retransmit

earlier data. The IR bit in the SiRIC does not change when an overrun error occurs.

When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every

time a reception is made.

When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is

transmitted on the falling edge of the transfer clock and received on the rising edge) and the external

clock is held "H" or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the

transfer clock and received on the falling edge) and the external clock is held "L", meet the following

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