M32CSLASH86 datasheet(492/505 Pages) RENESAS

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Page 469

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27.11 A/D Converter

• Set the AD0CON0 (bit 6 excluded), AD0CON1, AD0CON2, AD0CON3, and AD0CON4 registers while

the A/D conversion is stopped (before a trigger is generated).

• Wait a minimum of 1

µs before starting the A/D conversion when changing the VCUT bit setting in the

AD0CON1 register from "0" (VREF no connection) to "1" (VREF connection).

Change the VCUT bit setting from "1" to "0" after the A/D conversion is completed.

• Insert capacitors between the AVCC pin, VREF pin, analog input pin ANij (i=none, 0, 2, 15; j=0 to 7) and

AVSS pin to prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. The

same applies to the VCC and VSS pins. Figure 27.4 shows the use of capacitors to reduce noise.

27. Precautions (A/D Converter)

Microcomputer

NOTES:

1. C1

≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)

2. Use thick and shortest possible wiring to connect capacitors.

VCC

VSS

AVCC

AVSS

VREF

ANi

VCC

VSS

ANi: ANi, AN0i, AN15i and AN2i (i=0 to 7)

VCC

Figure 27.4 Use of Capacitors to Reduce Noise

• Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to

__________

"0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0"

(input mode) if the TRG bit in the AD0CON0 register is set to "1" (external trigger).

• When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input

interrupt request is generated when the A/D input voltage becomes "L").

• The

φAD frequency must be 16MHz or less. When the sample and hold function is not activated, the φAD

frequency must be 250 kHz or more. If the sample and hold function is activated, the

φAD frequency

must be 1MHz or more.

• Set the CH2 to CH0 bits in the AD0CON0 register or the SCAN1 and SCAN0 bits in the AD0CON1

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