M32CSLASH86 datasheet(494/505 Pages) RENESAS

494 / 505 page

Page 471

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27.12 Intelligent I/O

27.12.1 Register Setting

Operations, controlled by the values written to the G1BT, G1BCR1, G1TMCR0 to G1TMCR7, G1TPR6,

G1TPR7, G1TM0 to G1TM7, G1POCR0 to G1POCR7, G1PO0 to G1PO7, G1FS and G1FE registers,

are affected by the count source (fBT1) set in the BCK1 and BCK0 bits in the G1BCR0 register.

Set the BCK1 and BCK0 bits before setting the G1BT, G1BCR1, G1TMCR0 to G1TMCR7, G1TPR6,

G1TPR7, G1TM0 to G1TM7, G1POCR0 to G1POCR7, G1PO0 to G1PO7, G1FS and G1FE registers.

Operations, controlled by the values written to the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR,

G0RB and G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ETC, G0ERC and G1ERC,

G0IRF, G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1,

G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers are affected by the

transfer clock.

Set trasfer clock before setting the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR, G0RB and

G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ECT, G0ERC and G1ERC, G0IRF and

G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1,

G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers.

27. Precautions (Intelligent I/O)

M32C/86 Datasheet(PDF) 494 Page - Renesas Technology Corp