SH7750 datasheet(73/1162 Pages) RENESAS

73 / 1162 page

Rev.7.00 Oct. 10, 2008 Page lxxiii of lxxxiv

REJ09B0366-0700

Figure 18.6 MD1/TxD2 Pin....................................................................................................... 808

Figure 18.7 MD2/RxD2 Pin ...................................................................................................... 808

Figure 18.8

CTS2 Pin ................................................................................................................ 809

Figure 18.9 MD8/

RTS2 Pin....................................................................................................... 810

Section 19 Interrupt Controller (INTC)

Figure 19.1 Block Diagram of INTC......................................................................................... 826

Figure 19.2 Example of IRL Interrupt Connection.................................................................... 829

Figure 19.3 Interrupt Operation Flowchart ................................................................................ 844

Section 20 User Break Controller (UBC)

Figure 20.1 Block Diagram of User Break Controller............................................................... 852

Figure 20.2 User Break Debug Support Function Flowchart .................................................... 873

Section 21 High-performance User Debug Interface (H-UDI)

Figure 21.1 Block Diagram of H-UDI Circuit........................................................................... 880

Figure 21.2 TAP Control State Transition Diagram .................................................................. 891

Figure 21.3 H-UDI Reset........................................................................................................... 892

Section 22 Electrical Characteristics

Figure 22.1 EXTAL Clock Input Timing .................................................................................. 940

Figure 22.2 (1) CKIO Clock Output Timing ............................................................................. 940

Figure 22.2 (2) CKIO Clock Output Timing ............................................................................. 940

Figure 22.3 Power-On Oscillation Settling Time ...................................................................... 941

Figure 22.4 Standby Return Oscillation Settling Time (Return by

RESET) ............................. 941

Figure 22.5 Power-On Oscillation Settling Time ...................................................................... 942

Figure 22.6 Standby Return Oscillation Settling Time (Return by

RESET) ............................. 942

Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI).................................. 943

Figure 22.8 Standby Return Oscillation Settling Time (Return by

IRL3 to IRL0).................... 943

Figure 22.9 PLL Synchronization Settling Time in Case of

RESET or NMI Interrupt............. 944

Figure 22.10 PLL Synchronization Settling Time in Case of

IRL Interrupt................................ 944

Figure 22.11 Manual Reset Input Timing.................................................................................... 945

Figure 22.12 Mode Input Timing ................................................................................................ 945

Figure 22.13 Control Signal Timing............................................................................................ 948

Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode .................................................... 948

Figure 22.14 (2) Pin Drive Timing for Software Standby Mode ............................................... 949

Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)...................................................... 956

Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ...................................... 957

Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) .... 958

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