SH7760 datasheet(86/1345 Pages) RENESAS

86 / 1345 page

Rev. 1.0, 02/03, page 36 of 1294

Saved General Register 15 (SGR): The contents of R15 are saved to SGR in the event of an

exception or interrupt.

Debug Base Register (DBR): When the user break debugging function is enabled (BRCR.UBDE

= 1), DBR is referenced as the branch destination address of the user break handler instead of

VBR.

2.2.4

System Registers

The system registers are 32 bits long. They consist of two multiply-and-accumulate registers

(MACH and MACL), the procedure register (PR), the program counter (PC), the floating-point

status/control register (FPSCR), and the floating-point communication register (FPUL). For details

on FPSCR and FPUL, see section 3, Floating-Point Unit (FPU).

Multiply-and-Accumulate Registers (MACH and MACL): MACH and MACL are used for the

added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction.

Procedure Register (PR): The return address is stored in PR in a subroutine call using a BSR,

BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS).

Program Counter (PC): PC indicates the address of the instruction currently being executed.

2.2.5

FPU Registers

See section 3, Floating-Point Unit (FPU).

2.3

Memory-Mapped Registers

For details on the control registers mapped to memory, see section 32, List of Registers. The

control registers are double-mapped to the following two memory areas. All registers have two

addresses.

H'1C00 0000 to H'1FFF FFFF

H'FC00 0000 to H'FFFF FFFF

These two areas are used as follows.

• H'1C00 0000 to H'1FFF FFFF

This area must be accessed using the address translation function of the MMU.

Setting the page number of this area to the corresponding field of the TLB enables access to a

memory-mapped register.

The operation of an access to this area without using the address translation function of the

MMU is not guaranteed.

SH7760 Datasheet(PDF) 86 Page - Renesas Technology Corp