SH7760 datasheet(21/1345 Pages) RENESAS

21 / 1345 page

Rev. 1.0, 02/03, page xix of xlviii

23.3.2 Status Register (SPSR)......................................................................................... 828

23.3.3 System Control Register (SPSCR)....................................................................... 831

23.3.4 Transmit Buffer Register (SPTBR)...................................................................... 834

23.3.5 Receive Buffer Register (SPRBR) ....................................................................... 835

23.4

Operation........................................................................................................................... 836

23.4.1 Operation Overview without DMA (FIFO Mode Disabled)................................ 836

23.4.2 Operation Overview with DMA........................................................................... 837

23.4.3 Operation with FIFO Mode Enabled.................................................................... 837

23.4.4 Timing Diagrams ................................................................................................. 838

23.4.5 HSPI Software Reset............................................................................................ 839

23.4.6 Clock Polarity and Transmit Control ................................................................... 839

23.4.7 Transmit and Receive Routines ........................................................................... 839

23.5

Power Saving and Clocking Strategy................................................................................ 840

Section 24 Pin Function Controller (PFC)........................................................ 841

24.1

Features ............................................................................................................................. 841

24.2

Register Descriptions ........................................................................................................ 844

24.2.1 Port A Control Register (PACR).......................................................................... 847

24.2.2 Port B Control Register (PBCR) .......................................................................... 848

24.2.3 Port C Control Register (PCCR) .......................................................................... 849

24.2.4 Port D Control Register (PDCR).......................................................................... 850

24.2.5 Port E Control Register (PECR) .......................................................................... 852

24.2.6 Port F Control Register (PFCR)........................................................................... 853

24.2.7 Port G Control Register (PGCR).......................................................................... 854

24.2.8 Port H Control Register (PHCR).......................................................................... 855

24.2.9 Port J Control Register (PJCR) ............................................................................ 857

24.2.10 Port K Control Register (PKCR).......................................................................... 858

24.2.11 Port A Data Register (PADR) .............................................................................. 859

24.2.12 Port B Data Register (PBDR) .............................................................................. 860

24.2.13 Port C Data Register (PCDR) .............................................................................. 861

24.2.14 Port D Data Register (PDDR) .............................................................................. 861

24.2.15 Port E Data Register (PEDR)............................................................................... 862

24.2.16 Port F Data Register (PFDR) ............................................................................... 862

24.2.17 Port G Data Register (PGDR) .............................................................................. 863

24.2.18 Port H Data Register (PHDR) .............................................................................. 863

24.2.19 Port J Data Register (PJDR)................................................................................. 864

24.2.20 Port K Data Register (PKDR) .............................................................................. 864

24.2.21 GPIO Interrupt Control Register (GPIOIC) ......................................................... 865

24.2.22 Port A Pull-Up Control Register (PAPUPR) ....................................................... 867

24.2.23 Port B Pull-Up Control Register (PBPUPR)........................................................ 867

24.2.24 Port C Pull-Up Control Register (PCPUPR)........................................................ 868

24.2.25 Port D Pull-Up Control Register (PDPUPR) ....................................................... 869

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