TDA7503 datasheet(21/26 Pages) STMICROELECTRONICS

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64 x 24-Bit Boot ROM.

Serial Audio Interface (SAI) multiplexed to both

DSPs.

Synchronous Serial Interface (SSI) multiplexed

to both DSPs.

XCHG Interface for DSP to DSP communica-

tion.

Host Interface (HI) for DSP to Micro communi-

cation.

External Memory Interface (DRAM/SRAM)

multiplexed to both DSPs for time-delay.

Single Debug Port multiplexed to both DSPs.

Cordic Arithmetic Unit

DATA AND PROGRAM MEMORY

Both DSP0 and DSP1 have an identical set of

Data and Program memories attached them.

Each of the memories are described below and it

is implied that there are two of each type, one set

connected to DSP0 and the other to DSP1. The

only exception is the case of the P-RAM where

DSP0 has a 768 x 24-Bit PRAM and DSP1 has a

1280 x 24-Bit PRAM.

256 x 24-Bit X-RAM (XRAM)

This is a 256 x 24-Bit Single Port SRAM used for

storing coefficients. The 16-Bit XRAM address,

XABx(15:0) is generated by the Address Genera-

tion Unit of the DSP core. The 24-Bit XRAM Data,

XDBx(23:0), may be written to and read from the

Data ALU of the DSP core. The XDBx Bus is also

connected to the Internal Bus Switch so that it

can be routed to and from all peripheral blocks.

256 x 24 Bit Y-RAM (YRAM)

This is a 256 x 24-Bit Single Port SRAM used for

storing

coefficients.

The

16-Bit

address,

YABx(15:0) is generated by the Address Genera-

tion Unit of the DSP core. The 24-Bit Data,

YDBx(23:0), is written to and read from the Data

ALU of the DSP core. The YDBx Bus is also con-

nected to the Internal Bus Switch so that it can be

routed to and from other blocks.

768 x 24-Bit Program RAM (PRAM 1280 x 24-bit

for DSP1)

This is a 768 x 24-Bit Single Port SRAM used for

storing and executing program code. The 16-Bit

PRAM Address, PABx(15:0) is generated by the

Program Address Generator of the DSP core for

Instruction Fetching, and by the AGU in the case

of the Move Program Memory (MOVEM) Instruc-

tion. The 24-Bit PRAM Data (Program Code),

PDBx(23:0), can only be written to using the

MOVEM instruction. During instruction fetching

the PDBx Bus is routed to the Program Decode

Controller of the DSP core for instruction decod-

ing.

256 x 24-Bit X-ROM (XROM)

This is a 256 x 24-Bit factory programmed X-

ROM. The 16-Bit address, XABx(15:0) is gener-

ated by the AGU Unit. The 24-Bit Data is multi-

plexed onto the XDBx Bus when the address is

valid.

256 x 24-Bit Y-ROM (YROM)

This is a 256 x 24-Bit factory programmed Y-

ROM. The 16-Bit address, YABx(15:0) is gener-

ated by the AGU Unit. The 24-Bit Data is multi-

plexed onto the YDBx Bus when the address is

valid.

128 x 24-Bit Bootstrap ROM (PROM)

This is a 128 x 24-Bit factory programmed Boot

ROM used for storing the program sequence for

initializing the DSP. Essentially this consists of a

routine that is called when the M8051 requests

that a DSP image be sent via the Host Interface.

It is the task of the Boot code to read the data be-

ing sent by the micro from the Host Interface

FIFO and store it in PRAM, XRAM, YRAM, and/or

external DRAM.

Operating Mode Register

The operating mode register contains one bit to

choose between boot mode (always from the

Host Interface) or normal mode (execution from

PRAM). This bit will be set when the DSP is reset

(by writing to the RSDSPx bit in the CLKCNTL

enable execution from PRAM.

DSP Memory Maps

The DSP memory Maps are shown in Figure 26.

Serial Audio Interface (SAI)

The SAI is used to deliver digital audio to the

DSPs from an external source. Once processed

by the DSPs, it can be returned through this inter-

face. There is only one SAI on the chip that can

be accessed by either DSP. The features of the

SAI are listed below.

Five Synchronized Stereo Data Transmission

Lines

Four Synchronized Stereo Data Reception

Lines

Slave operating mode, all clock lines are in-

puts

TDA7503

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