TDA7503 datasheet(24/26 Pages) STMICROELECTRONICS

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achieved in software. When this mode is entered

instruction execution is switched to internal AUX-

RAM.

Serial Peripheral Interface

The 8051 core requires a serial interface to re-

ceive commands and data over the LAN. During

an SPI transfer, data is transmitted and received

simultaneously. A serial clock line synchronizes

shifting and sampling of the information on the

two serial data lines. A slave select line allows in-

dividual selection of a slave SPI device. The SS

Pin will act as a GPIO when the SPI is in master

mode or the SPI is disabled.

When an SPI transfer occurs an 8-bit word is

shifted out one data pin while another 8-bit char-

acter is simultaneously shifted in a second data

pin. The central element in the SPI system is the

shift register and the read data buffer. The sys-

tem is single buffered in the transfer direction and

double buffered in the receive direction.

Control Interface

The 8051 requires a set of external general pur-

pose input/output lines, two external interrupt

lines, and a reset line. These signals are used by

external devices to signal events to the 8051. The

GPIO lines are implemented as the 8051’s Port 1

GPIO. The two external interrupts are connected

to the INT0 and INT1 lines on the micro. The RE-

SET pin is used to reset the micro.

PLL Clock Oscillator

The PLL Clock Oscillator can accept an external

clock at XTI or it can be configured to run an in-

ternal oscillator when a crystal is connected

across pins XTI & XTO. There is an input divide

block IDF (1 -> 32) at the XTI clock input and a

multiply block MF (33 -> 128) in the PLL loop.

Hence the PLL can multiply the external input

clock by a ratio MF/IDF to generate the internal

clock. This allows the internal clock to be within 1

MHz of any desired frequency even when XTI is

much greater than 1 MHz. It is recommended that

the input clock is not divided down to less than 1

MHz as this reduces the Phase Detector’s update

rate.

The clocks to the DSP and the 8051 can be se-

lected to be either the VCO output divided by 2 or

4 respectively, or be driven by the XTI pin di-

rectly.

The crystal oscillator and the PLL will be gated off

when entering the power-down mode (by setting

bit 1 of the PCON Register).

M8051 Interrupts

The M8051 Core provides for 5 interrupt sources,

INT1, INT0, TIMER1, TIMER0, and SERIAL

Data. There exists a corresponding Interrupt En-

able register and Interrupt Priority Register.

TDA7503

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