TMS320C6745PTP2 datasheet(39/203 Pages) TI

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4.4 Pin Multiplexing Control Registers

TMS320C6745/6747 Floating-point Digital Signal Processor

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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008

completing the current operation then halting, or continuing operation. See the appropriate peripheral

documentation for specific details.

Since the SYSCFG peripheral controls global operation of the device, its registers are protected against

erroneous accesses by several mechanisms:

• A special key sequence must be written to KICK0, KICK1 registers before any other registers are

writeable.

–

Unlock sequence: write 0x83e70b13 to KICK0, then write 0x95A4F1E0 to KICK1

–

SYSCFG remains unlocked after the unlock sequence until locked again.

–

Any number of accesses may be performed while the module is unlocked

–

Locking the module is accomplished by writing any other value to either KICK0 or KICK1

• Additionally, many registers are accessible only by a host (DSP) when it is operating in its privileged

mode. (ex. from the kernel, but not from user space code).

Table 4-1. System Configuration (SYSCFG) Module Register Access

Offset

Acronym

Access

0x01C1 4000

REVID

Revision Identification Register

—

0x01C14008 –

DIEIDR0-DIEDR3

Device Identification Register 0 - 3

—

0x01C1 4014

0x01C1 4020

BOOTCFG

Boot Configuration Register

Privileged mode

0x01C1 4038

KICK0R

Kick 0 Register

Privileged mode

0x01C1 403C

KICK1R

Kick 1 Register

Privileged mode

0x01C1 4040

HOST0CFG

Host 0 Configuration Register

—

0x01C1 4044

HOST1CFG

Host 1 Configuration Register

—

0x01C1 40E0

IRAWSTAT

Interrupt Raw Status/Set Register

Privileged mode

0x01C1 40E4

IENSTAT

Interrupt Enable Status/Clear Register

Privileged mode

0x01C1 40E8

IENSET

Interrupt Enable Register

Privileged mode

0x01C1 40EC

IENCLR

Interrupt Enable Clear Register

Privileged mode

0x01C1 40F0

EOI

End of Interrupt Register

Privileged mode

0x01C1 40F4

FLTADDRR

Fault Address Register

Privileged mode

0x01C1 40F8

FLTSTAT

Fault Status Register

—

0x01C1

MSTPRI0-MSTPRI2

Master Priority 0-2 Registers

Privileged mode

4110-0x01C1 4118

0x01C1

PINMUX0-PINMUX19

Pin Multiplexing Control 0-19 Registers

Privileged mode

4120-0x01C1 416C

0x01C1 4170

SUSPSRC

Suspend Source Register

Privileged mode

0x01C1 4174

CHIPSIG

Chip Signal Register

—

0x01C1 4178

CHIPSIG_CLR

Chip Signal Clear Register

—

0x01C1

CFGCHIP0-CFGCHIP4

Chip Configuration 0-4 Registers

Privileged mode

417C-0x01C1

418C

Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.

For the 674x device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is

multiplexed with several different functions has a corresponding 4-bit field in one of the PINMUX registers.

Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data

and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'

of the peripheral functions in which case the pin's IO buffer is held tri-stated.

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TMS320C6745PTP2 Datasheet(PDF) 39 Page - Texas Instruments

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