AT83C24B-PRRIM datasheet(29/42 Pages) ATMEL

29 / 42 page

4234G–SCR–01/07

AT83C24

Electrical Characteristics

Absolute Maximum Ratings *

(**) Exposed die attached pad must be soldered to ground

Thermal resistor are measured on multilayer PCB with 0 m/s air flow.

(***) including shortages between any groups of smart card pins.

AC/DC Parameters EVCC connected to host power supply: from 1.6V to 5.5V.

TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V.

CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS

CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24B

CLASS B card supplied with CVCC = 2.8V to 3.2V

CLASS C card supplied with CVCC = 1.68V to 1.92V

Ambient Temperature Under Bias: .....................-40°C to 85°C

Storage Temperature: ................................... -65°C to +150°C

Voltage on VCC: ........................................ VSS -0.5V to +6.0V

Voltage on SCIB pins (***): ......... CVSS -0.5V to CVCC + 0.5V

Voltage on host interface pins:.......VSS -0.5V to EVCC + 0.5V

Voltage on other pins: ...................... VSS -0.5V to VCC + 0.5V

Power Dissipation: .......................................................... 1.5W

Thermal resistor of QFN pack-

age..(**)............................35°C/W

Thermal resistor of SO package.................................48°C/W

*NOTICE:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions above those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Power Dissipation value is based on the maxi-

mum allowable die temperature and the thermal

resistance of the package.

Table 17. Core (VCC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

PFDP

Power fail high level threshold

2.4

2.5

2.6

PFDM

Power fail low level threshold

2.25

2.35

2.45

rise, tfall

DD rise and fall time

1 µs

600s

Not tested.

Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Input Low-voltage

-0.5

0.3 x EVCC

0.25 x EVCC

EVCC from 2.7V to VCC

EVCC from 1.6 to 2.7V

Input High Voltage

0.7 x EVCC

EVCC + 0.5

EAUTO=0

EAUTO=1

EVCC from 1.6V to VCC

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