14

1772E–DRMSD–10-Apr-06

ATSAM9708

12.2

External Memory Timing Overview

One memory cycle consists of six internal master clock cycles (6 x t

clock period is one-fourth of the clock period at X1. The internal master clock is provided at pin

CK_OUT when external SDRAM is connected (RAS sensed high during RESET).

Figure 12-1. ROM and SRAM Basic Timing, DRAM = Low

Figure 12-2. DRAM Basic Timing, DRAM = High

Note:

1. See Table 12-1 on page 16.

012345

012345

0

12345

0

1

CK_OUT

WA[26:0]

WOE

WWE

RBS

WD

[15:0]

ROM/SRAM16 READ

SRAM16 WRITE

SRAM8 WRITE

012345

012345

0

12345

0

1

DRAxx

WD[15:0]

DRAM READ

DRAM WRITE

DRAM REFRESH

CAS

RAS

REFRESH

WWE

CK_OUT

(1)

row

col