AT80C51RA2-RLSIV datasheet(12/86 Pages) ATMEL

12 / 86 page

4188F–8051–01/08

AT/TS8xC51Rx2

5.2

TS80C51Rx2 Enhanced Features

In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which

are:

• The X2 option.

• The Dual Data Pointer.

• The extended RAM.

• The Programmable Counter Array (PCA).

• The Watchdog.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mode.

• The ALE disabling.

• Some enhanced features are also located in the UART and the timer 2.

5.3

X2 Feature

The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2”

provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Saves power consumption while keeping same CPU power (oscillator power saving).

• Saves power consumption by dividing dynamically operating frequency by 2 in operating and

idle modes.

• Increases CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-

nal and the main clock input of the core (phase generator). This divider may be disabled by

software.

5.3.1

Description

The clock for the whole circuit and peripheral is first divided by two before being used by the

CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2

mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to

60%. Figure 5-1 shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-

ing edge to avoid glitches when switching from X2 to STD mode. Figure 5-2 shows the mode

switching waveforms.

AT80C51RA2-RLSIV Datasheet(PDF) 12 Page - ATMEL Corporation