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A32100DXV-FPLC Datasheet(PDF) 78 Page - Actel Corporation |
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A32100DXV-FPLC Datasheet(HTML) 78 Page - Actel Corporation |
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78 / 84 page ![]() Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s 78 Discontinued – v3.0 Pa ckage P i n Assign me nts (continued) 176-Pin CPGA (Top View) 1 A 23456789 10 11 B C D E F G H J K L 176-Pin CPGA 123456789 10 11 12 12 13 13 14 14 15 15 M N P R A B C D E F G H J K L M N P R Signal Pad Number Location PRA or I/O 152 C9 PRB or I/O 160 D7 MODE 2 C3 SDI or I/O 135 B14 DCLK or I/O 175 B3 CLKA or I/O 154 A9 CLKB or I/O 158 B8 GND 1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89 101, 106, 111, 121, 126, 133, 145, 156, 165 D4, E4, G4, H4, K4, L4, M4, M6, M8, M10, M12 K12, J12, J13, H12, F12, E12, D12, D10, C8, D6 VCC 13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170 F4, H2, H3, J4, M5, N8, M11, J14, H13, H14, G12, D11, D8, D5 Notes: 1. Unused I/O pins are designated as outputs by ALS and are driven LOW. 2. All unassigned pins are available for use as I/Os. 3. MODE = GND, except during device programming or debugging. |
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