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A32100DXV-FPLC Datasheet(PDF) 29 Page - Actel Corporation

Part # A32100DXV-FPLC
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DXV-FPLC Datasheet(HTML) 29 Page - Actel Corporation

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Discontinued – v3.0
29
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
A122 5XL Timing Cha r ac teristics (continued)
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y High
1.1
1.2
1.4
2.0
1.7
ns
tINYL
Pad-to-Y Low
1.3
1.4
1.7
2.4
2.0
ns
tINGH
G-to-Y High
2.0
2.3
2.7
3.9
3.2
ns
tINGL
G-to-Y Low
2.6
3.0
3.5
5.0
4.2
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.9
3.3
3.9
5.6
4.7
ns
tIRD2
FO=2 Routing Delay
3.2
3.6
4.3
6.1
5.2
ns
tIRD3
FO=3 Routing Delay
3.8
4.2
5.0
7.2
6.0
ns
tIRD4
FO=4 Routing Delay
4.1
4.6
5.4
7.7
6.5
ns
tIRD8
FO=8 Routing Delay
5.2
5.9
6.9
9.9
8.3
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 256
5.1
5.7
5.8
6.5
6.8
7.6
9.7
10.9
8.2
9.1
ns
tCKL
Input High to Low
FO = 32
FO = 256
5.0
5.7
5.7
6.5
6.7
7.6
9.6
10.9
8.0
9.1
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 256
2.6
2.7
3.0
3.1
3.5
3.6
5.0
5.1
4.2
4.3
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 256
2.6
2.7
3.0
3.1
3.5
3.6
5.0
5.1
4.2
4.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
1.2
1.2
ns
tSUEXT
Input Latch External Set-Up
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
2.6
3.2
2.9
3.7
3.4
4.3
4.9
6.1
4.1
5.2
ns
tP
Minimum Period
FO = 32
FO = 256
5.4
5.6
6.1
6.3
7.2
7.4
10.3
10.6
8.6
8.9
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
225
200
200
180
170
155
120.
105
115
105
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.



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