AX2000-1CGG896 datasheet(78/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 64

v2.7

Functional Description

Figure 2-48 on page 2-63 illustrates a block diagram of

the PLL. The PLL contains two dividers, i and j, that allow

frequency scaling of the clock signal:

•

The i divider in the feedback path allows

multiplication of the input clock by integer factors

ranging from 1 to 64, and the resultant frequency

is available at the output of the PLL block.

•

The j divider divides the PLL output by integer

factors ranging from 1 to 64, and the divided clock

is available at CLK1.

•

The two dividers together can implement any

combination of multiplication and division up to a

maximum frequency of 1 GHz on CLK1. Both the

CLK1 and CLK2 outputs have a fixed 50/50 duty

cycle.

•

The output frequencies of the two clocks are given

by the following formulas (fREF is the reference

clock frequency):

fCLK1 = fREF * (DividerI) / (DividerJ)

EQ 2-4

fCLK2 = fREF * (DividerI)

EQ 2-5

•

CLK2 provides the PLL output directly—without

division

The input and output frequency ranges are selected by

LowFreq and Osc(2:0), respectively. These functions and

their possible values are detailed in Table 2-79.

The delay lines shown in Figure 2-48 on page 2-63 are

programmable. The feedback clock path can be delayed

(using the five DelayLine bits) relative to the reference

clock (or vice versa) by up to 3.75 ns in increments of

250 ps. Table 2-79 describes the usage of these bits. The

delay increments are independent of frequency, so this

results in phase changes that vary with frequency. The

delay value is highly dependent on VCC and the speed

grade.

Figure 2-49 on page 2-65 is a logical diagram of the

various control signals to the PLL and shows how the PLL

interfaces with the global and routing networks of the

FPGA. Note that not all signals are user-accessible. These

non-user-accessible signals are used by Actel's place-and-

route tool to control the configuration of the PLL. The

user gains access to these control signals either based

upon the connections built in the user's design or

through the special macros (Table 2-83 on page 2-67)

inserted into the design. For example, connecting the

macro PLLOUT to CLK2 will control the OUTSEL signal.

Table 2-79 • PLL Interface Signals

Signal Name

Type

User Accessible

Allowable Values

Function

RefCLK

Input

Yes

Reference Clock for the PLL

Input

Yes

Feedback port for the PLL

PowerDown

Input

Yes

PLL power down control

PLL powered down

PLL active

DIVI[5:0]

Input

Yes

1 to 64, in unsigned

binary notation offset

by -1

Sets value for feedback divider (multiplier)

DIVJ[5:0]

Input

Yes

Sets value for CLK1 divider

LowFreq

Input

Yes

Input frequency range selector

50–200 MHz

14–50 MHz

Osc[2:0]

Input

Yes

Output frequency range selector

XX0

400–1000 MHZ

001

200–400 MHZ

011

100–200 MHZ

101

50–100 MHZ

111

20–50 MHZ

DelayLine[4:0]

Input

Yes

–15 to +15

(increments), in signed-

and-magnitude binary

representation

Clock Delay (positive/negative) in increments of 250 ps, with

maximum value of ± 3.75 ns

FBMuxSel

Input

Selects the source for the feedback input

REFSEL

Input

Selects the source for the reference clock

OUTSEL

Input

Selects the source for the routed net output

AX2000-1CGG896 Datasheet(PDF) 78 Page - Actel Corporation

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