LTC1760CFW datasheet(37/44 Pages) LINER

37 / 44 page

LTC1760

1760f

is essentially DC. CB2 is the primary filter capacitor and

CB1 is used to provide a zero in the response to cancel the

pole associated with CB2. Acceptable voltage ripple at VSET

is about 10mVP-P. Since the period of the delta-sigma

switch closure, T∆Σ, is about 11µs and the internal VDAC

resistor, RVSET, is 7.2kΩ, the ripple voltage can be ap-

proximated by:

∆

VSET

REF

VSET

()

∑

•

Then the equation to extract CB1 || CB2 is:

REF

VSET

•

∑

∆

CB2 should be 10× to 20× CB1 to divide the ripple voltage

present at the charger output. Therefore CB1 = 0.01µF and

CB2 = 0.1µF are good starting values. In order to prevent

overshoot during start-up transients the time constant

associated with CB2 must be shorter than the time constant

of C5 at the ITH pin. If CB2 is increased to improve ripple

rejection, then C5 should be increased proportionally and

charger response time to voltage variation will degrade.

Input and Output Capacitors

In the 4A Lithium Battery Charger (Typical Application

section), the input capacitor (CIN) is assumed to absorb all

input switching ripple current in the converter, so it must

have adequate ripple current rating. Worst-case RMS

ripple current will be equal to one half of output charging

current. Actual capacitance value is not critical. Solid

tantalum low ESR capacitors have high ripple current

rating in a relatively small surface mount package,

but

caution must be used when tantalum capacitors are used

for input or output bypass. High input surge currents can

be created when the adapter is hot-plugged to the charger

or when a battery is connected to the charger. Solid

tantalum capacitors have a known failure mechanism

when subjected to very high turn-on surge currents. Only

Kemet T495 series of “Surge Robust” low ESR tantalums

are rated for high surge conditions such as battery to

ground.

APPLICATIO S I FOR ATIO

Calculating IC Power Dissipation

The power dissipation of the LTC1760 is dependent upon

the gate charge of QTG and QBG.(Refer to Typical

Application). The gate charge is determined from the

manufacturer’s data sheet and is dependent upon both the

gate voltage swing and the drain voltage swing of the FET.

PD = (VDCIN – VVCC) • fOSC • (QTG + QBG) + VDCIN •

IDCIN_CHG – VVCC • (ISAFETY1 + ISAFETY2)

where:

IDCIN_CHG, ISAFETY1, ISAFETY2 are defined in the

previous section.

Example:

VVCC = 5.2V, VDCIN = 19V, fOSC = 345kHz, QTG =

QBG = 15nC, IDCIN_CHG = 2.62mA, ISAFETY1 =

ISAFETY2 = 218µA.

PD = 190mW

VSET/ISET Capacitors

Capacitor C7 is used to filter the delta-sigma modulation

frequency components to a level which is essentially DC.

Acceptable voltage ripple at ISET is about 10mVP-P. Since

the period of the delta-sigma switch closure, T∆Σ, is about

10µs and the internal IDAC resistor, RSET, is 18.77k, the

ripple voltage can be approximated by:

∆

ISET

REF

SET

∑

•

•7

Then the equation to extract C7 is:

REF

ISET

SET

7 =

∑

•

∆

= 0.8/0.01/18.77k(10µs) ≅ 0.043µF

In order to prevent overshoot during start-up transients

the time constant associated with C7 must be shorter than

the time constant of C5 at the ITH pin. If C7 is increased to

improve ripple rejection, then C5 should be increased

proportionally and charger response time to average cur-

rent variation will degrade.

Capacitors CB1 and CB2 are used to filter the VDAC delta-

sigma modulation frequency components to a level which

LTC1760CFW Datasheet(PDF) 37 Page - Linear Technology

LTC1760CFW Datasheet(HTML) 37 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL