TCM320AC36, TCM320AC37

VOICE-BAND AUDIO PROCESSORS (VBAP

™)

SLWS003C – MAY 1992 – REVISED APRIL – 1998

10

POST OFFICE BOX 655303

timing requirements

clock timing requirements over recommended ranges of supply voltage and operating free-air temperature

(see Figure 1 through Figure 4)

MIN

NOM†

MAX

UNIT

tt

Transition time, CLK and DCLKX /DCLKR

10

ns

Duty cycle, CLK

45%

50%

55%

Duty cycle, DCLKX /DCLKR

45%

50%

55%

† All typical values are at VCC = 5 V, TA = 25°C.

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 2)

MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before CLK

↓

20

468

ns

th(FSX)

Hold time, FSX high after CLK

↓

20

468

ns

receive timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 1)

MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before CLK

↓

20

468

ns

th(FSR)

Hold time, FSR high after CLK

↓

20

468

ns

tsu(DIN)

Setup time, DIN high or low before CLK

↓

20

ns

th(DIN)

Hold time, DIN high or low after CLK

↓

20

ns

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode (see Figure 4)

MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before DCLKX

↓

40

tc(DCLKX)–40

ns

th(FSX)

Hold time, FSX high after DCLKX

↓

35

tc(DCLKX)–35

ns

receive timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode (see Figure 3)

MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before DCLKR

↓

40

ns

th(FSR)

Hold time, FSR high after DCLKR

↓

35

tc(DCLKR)–35

ns

tsu(DIN)

Setup time, DIN high or low before DCLKR

↓

30

ns

th(DIN)

Hold time, DIN high or low after DCLKR

↓

30

ns

switching characteristics

propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd1

From CLK bit 1 high to DOUT bit 1 valid

35

ns

tpd2

From CLK high to DOUT valid, bits 2 to n

35

ns

tpd3

From CLK bit n low to DOUT bit n Hi-Z

30

ns

tpd4

From CLK bit 1 high to TSX active (low)

Rpullup = 1.24 kΩ

40

ns

tpd5

From CLK bit n low to TSX inactive (high)

Rpullup = 1.24 kΩ

30

ns