TCM320AC36, TCM320AC37

VOICE-BAND AUDIO PROCESSORS (VBAP

™)

SLWS003C – MAY 1992 – REVISED APRIL – 1998

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Table 1. Power-Down and Standby Procedures

DEVICE STATUS

PROCEDURE

TYPICAL POWER

CONSUMPTION

DIGITAL OUTPUT STATUS

Power on

PDN = high,

FSX = pulses,

FSR = pulses

40 mW

Digital outputs active but not loaded

Power down

PDN = low,

FSX, FSR = X†

3 mW

TSX and DOUT in the high-impedance state

Entire device on standby

mode

FSX = low,

FSR = low,

PDN = high

5 mW

TSX and DOUT in the high-impedance state

Only transmit channel in

standby mode

FSX = low,

FSR = pulses,

PDN = high

20 mW

TSX and DOUT in the high-impedance state within five

frames

Only receive channel in

standby mode

FSR = low,

FSX = pulses,

PDN = high

20 mW

Digital outputs active but not loaded

† X = don’t care

fixed-data-rate timing

synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling

frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data

is received on DIN on the falling edges of CLK following FSR. A D/A conversion is performed on the received

digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred

to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode.

variable-data-rate timing

Variable-data-rate timing is selected by connecting DCLKR to the receive data clock. In this mode, the master

clock (CLK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled

by DCLKR and DCLKX respectively. This allows the data to be transferred in and out of the device at any rate

up to the frequency of the master clock. DCLKR and DCLKX must be synchronous with CLK.

While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DCLKX.

Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of

DCLKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as

DCLKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than

once per frame, is available only with variable-data-rate timing.

asynchronous operations

To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters,

filters, and voltage references on the transmit and receive sides. This allows completely independent operation

of the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be

synchronized at the beginning of each frame.

precision voltage references

A precision band-gap reference voltage is generated internally and is used to supply all the references required

for operation of both the transmit and receive channels. The gain in each channel is trimmed during the

manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage

and device temperature.