TLV320AD11A

3.3 V INTEGRATED ADSL OVER POTS CODEC

SLWS087B – JUNE 1999 – REVISED MARCH 2000

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POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

communication channels (continued)

clock generation

The clock generation block provides the necessary clock signals for the device, with minimum skew and jitter.

This is closely dependent on the performance of the external VCXO. The external VCXO specifications are:

The major clocks generated internally are shown in Table 1.

Table 1. Clock Description

CLOCK

FREQUENCY

(MHz)

OSEN=0

OSEN=1

INT

2.208

4.416

CLKOUT

4.416

4.416

SCLK

4.416

4.416

INT

The interrupt (INT) to the host processor is 4.416 MHz when OSEN = 1 and 2.208 MHz when OSEN = 0.

SCLK

The serial clock used in the serial codec interface has a fixed frequency of 4.416 MHz and is synchronous with

the master clock (35.328 MHz).

CLKOUT

CLKOUT is a 4.416-MHz clock output, and is synchronous with the master clock (35.328 MHz).

interface

parallel interface

The device has a 16-bit parallel interface for transmitter and receiver data. Strobes OE, WETX, and CS from

the host DSP are edge-triggered signals. An incoming signal is registered on the rising edge of WETX/WEEC.

When ONE_WE is enabled, only WETX is needed for both the transmit channel and the echo-cancellation

channel write operation. After D0 of register SCR14 is programmed, the data from the first pulse of WETX goes

to the transmit channel, while the data from the second pulse of WETX goes to the echo-cancellation channel.

Output data from the codec is enabled after the falling edge of the OE strobe, and disabled after the rising edge

of the OE strobe. The INT cycle time is hardware-configurable to 4.416 MHz (2X over-sampling mode,

OSEN=1), or to 2.208 MHz (1X over-sampling mode, OSEN=0). SYNC is used to synchronize the operation

between the codec and the host transceiver. SCLK/READY is used to indicate the parallel data transfer period

in configuration mode 2. See Figure 3 for details.

OE_SYNC is used to synchronize the codec timing to OE. See Figure 5 for details.

For the 16-bit parallel data, D0 is the LSB and D15 is the MSB. The parallel TX and RX data contains 16 valid

bits. All 16 bits are used in the digital filtering.