TMS320VC5421 datasheet(40/88 Pages) TI

40 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PLL clock programmable timer

During the lockup period, the PLL should not be used to clock the ’5421. The PLLCOUNT programmable lock

timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is

achieved.

The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from

its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided

by 16. The resulting lockup delay can therefore be set from 0 to 255

× 16 CLKIN cycles.

The lock timer is activated when the operating mode of the clock generator is switched from DIV to PLL. During

the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer decrements

to zero, the PLL begins clocking the ’5421.

Accordingly, the value loaded into PLLCOUNT is chosen based on the following formula:

PLLCOUNT

Lockup Time

CLKIN

where TCLKIN is the input reference clock period and lockup time is the required VCO lockup time, as shown in

Table 17.

Table 17. VCO Lockup Time

CLKOUT FREQUENCY (MHz)

LOCKUP TIME (

µs)

100

TMS320VC5421 Datasheet(PDF) 40 Page - Texas Instruments