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TMS320VC5421 Datasheet(PDF) 48 Page - Texas Instruments

Part # TMS320VC5421
Description  DIGITAL SIGNAL PROCESSOR
PDF  88 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5421 Datasheet(HTML) 48 Page - Texas Instruments

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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
interrupts (continued)
Table 23. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
15
Reserved
X
Register bit is reserved.
14
IPINT
0
IFR/IMR: Interprocessor IRQ has no interrupt pending/is disabled (masked).
14
IPINT
1
IFR/IMR: Interprocessor IRQ has an interrupt pending/is enabled.
13
DMAC5
0
IFR/IMR: DMA Channel 5 has no interrupt pending/is disabled (masked).
13
DMAC5
1
IFR/IMR: DMA Channel 5 has an interrupt pending/is enabled.
12
DMAC4
0
IFR/IMR: DMA Channel 4 has no interrupt pending/is disabled (masked).
12
DMAC4
1
IFR/IMR: DMA Channel 4 has an interrupt pending/is enabled.
XINT1
0
IFR/IMR: McBSP_1 has no transmit interrupt pending/is disabled (masked).
11
XINT1
1
IFR/IMR: McBSP_1 has a transmit interrupt pending/is enabled.
11
DMAC3
0
IFR/IMR: DMA Channel 3 has no interrupt pending/is disabled (masked).
DMAC3
1
IFR/IMR: DMA Channel 3 has an interrupt pending/is enabled.
RINT1
0
IFR/IMR: McBSP_1 has no receive interrupt pending/is disabled (masked).
10
RINT1
1
IFR/IMR: McBSP_1 has a receive interrupt pending/is enabled.
10
DMAC2
0
IFR/IMR: DMA Channel 2 has no interrupt pending/is disabled (masked).
DMAC2
1
IFR/IMR: DMA Channel 2 has an interrupt pending/is enabled.
9
HPINT
0
IFR/IMR: Host-port interface has no DSPINT interrupt pending/is disabled (masked).
9
HPINT
1
IFR/IMR: Host-port interface has an DSPINT interrupt pending/is enabled.
8
Reserved
X
Register bit is reserved.
XINT2
0
IFR/IMR: McBSP_2 has no transmit interrupt pending/is disabled (masked).
7
XINT2
1
IFR/IMR: McBSP_2 has a transmit interrupt pending/is enabled.
7
DMAC1
0
IFR/IMR: DMA Channel 1 has no interrupt pending/is disabled (masked).
DMAC1
1
IFR/IMR: DMA Channel 1 has an interrupt pending/is enabled.
RINT2
0
IFR/IMR: McBSP_2 has no receive interrupt pending/is disabled (masked).
6
RINT2
1
IFR/IMR: McBSP_2 has a receive interrupt pending/is enabled.
6
DMAC0
0
IFR/IMR: DMA Channel 0 has no interrupt pending/is disabled (masked).
DMAC0
1
IFR/IMR: DMA Channel 0 has an interrupt pending/is enabled.
5
XINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
5
XINT0
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
4
RINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
4
RINT0
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
3
TINT
0
IFR/IMR: Timer has no interrupt pending/is disabled (masked).
3
TINT
1
IFR/IMR: Timer has an interrupt pending/is enabled.
2
Reserved
X
Register bit is reserved.
1
INT1
0
IFR/IMR: Ext user interrupt pin 1 has no interrupt pending/is disabled (masked).
1
INT1
1
IFR/IMR: Ext user interrupt pin 1 has an interrupt pending/is enabled.
0
INT0
0
IFR/IMR: Ext user interrupt pin 0 has no interrupt pending/is disabled (masked).
0
INT0
1
IFR/IMR: Ext user interrupt pin 0 has an interrupt pending/is enabled.



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