November 2006

ASM2P2351AH

rev 0.3

Notice: The information in this document is subject to change without notice.

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

1-Line To 10-Line Clock Driver With 3-State Outputs

Features

•

Low Output Skew, Low Pulse Skew for Clock-

Distribution and Clock-Generation Applications.

•

•

LVTTL-Compatible Inputs and Outputs.

•

Supports Mixed-Mode Signal Operation.

(5V Input and Output Voltages With 3.3V Supply

Voltage).

•

Distributes One Clock Input to Ten Outputs.

•

Outputs have Internal Series Damping Resistor

to Reduce Transmission Line Effects.

•

Switching Noise.

•

Package Options Include Plastic Small-Outline

and Shrink Small-Outline Packages.

Product Description

The ASM2P2351AH is a high-performance clock-driver

circuit that distributes one input (A) to ten outputs (Y)

with minimum skew for clock distribution. The output-

enable (OE) input disables the outputs to a high-

impedance state. Each output has an internal series

damping resistor to improve signal integrity at the load.

The ASM2P2351AH operates at nominal 3.3V Supply

Voltage.

The propagation delays are adjusted at the factory

using the P0 and P1 pins. The factory adjustments

ensure that the part-to-part skew is minimized and is

kept within a specified window. Pins P0 and P1 are not

intended for customer use and should be connected to

GND.

The ASM2P2351AH is characterized for operation

from 0

Pin Configuration

Logic Diagram (Positive Logic)

5

OE

6

PO P1

7 8

A

23

21

19

18

16

14

11

9

4

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y10

2

Y3

OE

Y7

GND

Y6

Y4

Y2

Y1

GND

Y5

GND

Y10

GND

Y9

A

P0

P1

GND

GND

ASM2P2351AH

1

2

3

4

5

6

7

8

9

10

11

12

17

18

19

20

21

22

23

24

Y8

13

14

15

16