CY7C024AV-25AI datasheet(15/19 Pages) CYPRESS

Part #	CY7C024AV-25AI

Description	3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

PDF	19 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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15 / 19 page

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J

Page 15 of 19

Note

48. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.

Switching Waveforms (continued)

ADDRESS MATCH

tPS

tBLC

tBHC

ADDRESS MATCH

tPS

tBLC

tBHC

CER ValidFirst:

ADDRESS L,R

BUSYR

CEL

CER

BUSYL

CER

CE L

ADDRESS L,R

Figure 14. Busy Timing Diagram No.1 (CE Arbitration)[48]

CELValid First

ADDRESS MATCH

tPS

ADDRESS L

BUSY R

ADDRESS MISMATCH

tRC or tWC

tBLA

tBHA

ADDRESSR

ADDRESS MATCH

ADDRESS MISMATCH

tPS

ADDRESSL

BUSY L

tRC or tWC

tBLA

tBHA

ADDRESSR

Right Address Valid First:

Figure 15. Busy Timing Diagram No.2 (Address Arbitration)[48]

Left Address Valid First:

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