TMC1175A datasheet(2/18 Pages) CADEKA

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TMC1175A

PRODUCT SPECIFICATION

REV. 1.3.3 2/28/02

Functional Description

The TMC1175A 8-bit A/D converter uses a two-step archi-

tecture to perform analog-to-digital conversion at rates up to

40 Msps. The input signal is held in an integral track/hold

stage during the conversion process. Operation is pipelined,

with one input sample taken and one output word provided

for each CONVert cycle.

The ﬁrst step in the conversion process is a coarse 4-bit

quantization. This determines the range of the subsequent

ﬁne 4-bit quantization step. To eliminate spurious codes, the

ﬁne 4-bit A/D quantizer output is gray-coded and converted

to binary before it is combined with the coarse result to form

a complete 8-bit result.

Analog Input and Voltage References

The TMC1175A converts analog signals in the range RB to

RT into digital data. Input signals outside that range produce

“saturated” 00h or FFh output codes. The device will not be

damaged by signals within the range AGND to VDDA.

Input voltage range is very ﬂexible and extends from the +5

Volt power supply to ground. Performance is speciﬁed over

the optimom 2 volt input range: 0.6V to 2.6V. However, the

part will function with a full-scale range from 1.0V to 5.0V.

A reduced input range may simplify analog signal condition-

ing circuitry, at the expense of additional noise sensitivity

and reduced differential linearity. Increasing the range can

improve differential linearity, but imposes a greater burden

on the input signal conditioning circuitry.

In many applications, external voltage reference sources are

connected to the RT and RB pins. RB can be grounded. Gain

and offset errors are directly related to the accuracy and sta-

bility of the applied reference voltages.

Two reference pull-up and pull-down resistors connected to

VR+ and VR– are provided internally for operation without

external voltage reference circuitry (Figure 1). The reference

voltages applied to RT and RB may be generated by connect-

ing VR+ to RT and VR- to RB. The power supply voltage is

divided by the on-chip resistors to bias the RT and RB points.

This sets-up the converter for operation in its nominal range

from 0.6V to 2.6V.

Figure 1. Reference Resistors

With VDDA at 5.0V, connecting VR+ to RT and grounding

RB will provide an input range from 0.0V to 2.27V, while

connecting RT to VDDA and RB to VR- produces a full scale

range of 3.85V referenced to VDDA. External resistors may

also be employed to provide arbitrary reference voltages, but

they will not match the temperature coefﬁcient of the on-

chip resistors as well as R+ and R-, and will cause the con-

verter transfer function to vary with temperature.

With this implementation, errors in the power supply voltage

end up on the conversion data output.

Because a two-step conversion process is employed, it is

important that the references remain stable during the

ENTIRE conversion process (two clock cycles). The refer-

ence voltage can then be changed, but any conversion in

progress during a reference change is invalid.

VDDA

VR+

R+

324

Ω

RREF

270

Ω

R–

Ω

VR–

+2.6V

+0.6V

27010A

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