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STM32W108HB Datasheet(PDF) 70 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 70 Page - STMicroelectronics |
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70 / 179 page  Serial interfaces STM32W108CB, STM32W108HB 70/179 Doc ID 16252 Rev 2 7.5.3 TWI control 2 register (SCx_TWICTRL2) Address offset: 0xC850 (SC1_TWICTRL2) and 0xC050 (SC2_TWICTRL2) Reset value: 0x0000 0000 7.6 Universal asynchronous receiver / transmitter (UART) registers Refer to the SPI Master mode section for a description of the SCx_DATA register. 7.6.1 UART status register (SC1_UARTSTAT) Address offset: 0xC848 Reset value: 0x0000 0040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_T WIACK rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [0] SC_TWIACK: Setting this bit signals ACK after a received byte. Clearing this bit signals NACK after a received byte. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_UA RTTXI DLE SC_UA RTPAR ERR SC_U ARTF RMER R SC_UA RTRX OVF SC_UA RTTXF REE SC_UA RTRXV AL SC_UA RTCTS rw rw rw rw rw rw rw rw rw r r r r r r r [6] SC_UARTTXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are empty. [5] SC_UARTPARERR: This bit is set when the byte in the data register was received with a parity error. This bit is updated when the data register is read, and is cleared if the receive FIFO is empty. [4] SC_UARTFRMERR: This bit is set when the byte in the data register was received with a frame error. This bit is updated when the data register is read, and is cleared if the receive FIFO is empty. [3] SC_UARTRXOVF: This bit is set when the receive FIFO has been overrun. This occurs if a byte is received when the receive FIFO is full. This bit is cleared by reading the data register. |
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