STM32W108HB datasheet(82/179 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108CB, STM32W108HB

82/179

Doc ID 16252 Rev 2

The GPIOs that can be used by Timer 1 are fixed, but the GPIOs that can be used as Timer

2 channels can be mapped to either of two pins, as shown in Table 11. The Timer 2 Option

2 channel is mapped to its default GPIO in port PA, or remapped to a GPIO in PB.

Table 11 specifies the pins that may be assigned to Timer 1 and Timer 2 functions.

The TIMxCLK and TIMxMSK inputs can be used only in the external clock modes: refer to

the External Clock Source Mode 1 and External Clock Source Mode 2 sections for details

concerning their use.

8.1.1

Time-base unit

The main block of the general purpose timer is a 16-bit counter with its related auto-reload

be divided by a prescaler.

The counter, the auto-reload register, and the prescaler register can be written to or read by

software. This is true even when the counter is running.

The time-base unit includes:

●

Counter register (TIMx_CNT)

●

Prescaler register (TIMx_PSC)

●

Auto-reload register (TIMx_ARR)

Some timer registers cannot be directly accessed by software, which instead reads and

writes a "buffer register". The internal registers actually used for timer operations are called

"shadow registers".

The auto-reload register is buffered. Writing to or reading from the auto-reload register

accesses the buffer register. The contents of the buffer register are transferred into the

shadow register permanently or at each update event (UEV), depending on the auto-reload

buffer enable bit (TIM_ARBE) in the TIMx_CR1 register. The update event is generated

when both the counter reaches the overflow (or underflow when down-counting) and when

the TIM_UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software.

Update event generation is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the

counter enable bit (TIM_CEN) in the TIMx_CR1 register is set. Refer also to the slave mode

controller description in the Timers and External Trigger Synchronization section to get more

details on counter enabling.

Note that the actual counter enable signal CNT_EN is set one clock cycle after TIM_CEN.

Table 11.

Timer GPIO use

Signal (direction)

TIMxC1

(in or out)

TIMxC2

(in or out)

TIMxC3

(in or out)

TIMxC4

(in or out)

TIMxCLK

(in)

TIMxMSK

(in)

Timer 1

PB6

PB7

PA6

PA7

PB0

PB5

Timer 2

(TIM_REMAPCy = 0)

PA0

PA3

PA1

PA2

PB5

PB0

Timer 2

(TIM_REMAPCy = 1)

PB1

PB2

PB3

PB4

PB5

PB0

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