MRF24J40-ISLASHML datasheet(35/152 Pages) MICROCHIP

35 / 152 page

Preliminary

DS39776B-page 33

MRF24J40

TXNCON: TRANSMIT NORMAL FIFO CONTROL REGISTER (ADDRESS: 0x1B)

R/W-0

R-0

R/W-0

W-0

FPSTAT(1) INDIRECT(4) TXNACKREQ(2,4) TXNSECEN(3,4)

TXNTRIG

bit 7

bit 0

Legend:

r = reserved

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

Reserved: Maintain as ‘0’

bit 4

FPSTAT: Frame Pending Status bit(1)

Status of the frame pending bit in the received Acknowledgement frame.

= Frame pending bit = 1

= Frame pending bit = 0

bit 3

INDIRECT: Activate Indirect Transmission bit (coordinator only)(4)

= Indirect transmission enabled

= Indirect transmission disabled (default)

bit 2

TXNACKREQ: TX Normal FIFO Acknowledgement Request bit(2,4)

Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received,

retransmit.

= Acknowledgement requested

= No Acknowledgement requested (default)

bit 1

TXNSECEN: TX Normal FIFO Security Enabled bit(3,4)

= Security enabled

= Security disabled (default)

bit 0

TXNTRIG: Transmit Frame in TX Normal FIFO bit

= Transmit the frame in the TX Normal FIFO; bit is automatically cleared by hardware

Note 1:

Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield”.

Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.4 “Acknowledgement Request Subfield”.

Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.2 “Security Enabled Subfield”.

Bit is cleared at the next triggering of TXN FIFO.

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