PIC18F44J10 datasheet(161/368 Pages) MICROCHIP

161 / 368 page

DS39682E-page 159

PIC18F45J10 FAMILY

16.4

I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCLx) – RC3/SCK1/SCL1 or

RD6/SCK2/SCL2

• Serial data (SDAx) – RC4/SDI1/SDA1 or

RD5/SDI2/SDA2

The user must configure these pins as inputs by setting

the associated TRIS bits.

FIGURE 16-7:

MSSP BLOCK DIAGRAM

(I2C™ MODE)

16.4.1

REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register 1 (SSPxCON1)

• MSSP Control Register 2 (SSPxCON2)

• MSSP Status Register (SSPxSTAT)

• Serial Receive/Transmit Buffer Register

(SSPxBUF)

• MSSP Shift Register (SSPxSR) – Not directly

accessible

• MSSP Address Register (SSPxADD)

SSPxCON1, SSPxCON2 and SSPxSTAT are the

control and status registers in I2C mode operation. The

SSPxCON1 and SSPxCON2 registers are readable

and writable. The lower 6 bits of the SSPxSTAT are

read-only. The upper two bits of the SSPxSTAT are

read/write.

Many of the bits in SSPxCON2 assume different

functions, depending on whether the module is operat-

ing in Master or Slave mode; bits<5:2> also assume

different names in Slave mode. The different aspects of

SSPxCON2 are shown in Register 16-5 (for Master

mode) and Register 16-6 (Slave mode).

SSPxSR is the shift register used for shifting data in or

out. SSPxBUF is the buffer register to which data bytes

are written to or read from.

SSPxADD register holds the slave device address

when the MSSP is configured in I2C Slave mode. When

the MSSP is configured in Master mode, the lower

seven bits of SSPxADD act as the Baud Rate

Generator reload value.

In receive operations, SSPxSR and SSPxBUF together

create a double-buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

During

transmission,

the

SSPxBUF

not

double-buffered. A write to SSPxBUF will write to both

SSPxBUF and SSPxSR.

Read

Write

SSPxSR reg

Match Detect

SSPxADD reg

SSPxBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPxSTAT reg)

Shift

Clock

MSb

LSb

Note:

Only port I/O names are used in this diagram for

the sake of brevity. Refer to the text for a full list of

multiplexed functions.

SCLx

SDAx

Start and

Stop bit Detect

Address Mask

Note:

Disabling the MSSP module by clearing

the SSPEN (SSPxCON1<5>) bit may not

reset the module. It is recommended to

clear the SSPxSTAT, SSPxCON1 and

SSPxCON2 registers and select the mode

prior to setting the SSPEN bit to enable

the MSSP module.

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