EDD51163DBH-LS datasheet(13/60 Pages) ELPIDA

13 / 60 page

EDD51163DBH-LS

Preliminary Data Sheet E1433E30 (Ver. 3.0)

Pin Function

CK, /CK (input pins)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross

point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the

cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS

and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other

input signals are referred at CK rising edge.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See "Command operation".

A0 to A12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the

/CK falling edge in a bank active command cycle. Column address is loaded at the cross point of the CK rising edge

and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This column address

becomes the starting address of a burst operation.

[Address Pins Table]

Address (A0 to A12)

Part number

Page size

Organization

Row address

Column address

EDD51163DBH

2KB

× 16 bits

AX0 to AX12

AY0 to AY9

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge

command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write

command, auto precharge function is enabled.

BA0 and BA1 (input pins)

BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.

(See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

BA1

Bank 0

Bank 1

Bank 2

Bank 3

Remark: H: VIH. L: VIL.

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