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P89CV51RB2 Datasheet(PDF) 13 Page - NXP Semiconductors |
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P89CV51RB2 Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 76 page ![]() P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 25 August 2009 13 of 76 NXP Semiconductors P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI 6.2 Memory organization The various P89CV51RB2/RC2/RD2 memory spaces are as follows: • DATA 128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the stack may be in this area. • IDATA Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the stack may be in this area. This area includes the DATA area and the 128 B immediately above it. • SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. • XDATA ‘External’ Data or auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. The P89CV51RB2/RC2/RD2 have 768 B of on-chip XDATA memory. • CODE 64 kB of code memory space, accessed as part of program execution and via the MOVC instruction. The P89CV51RB2/RC2/RD2 have 16/32/64 kB of on-chip code memory. 6.2.1 Expanded data RAM addressing The P89CV51RB2/RC2/RD2 have 1 kB of data RAM; see Figure 4. To access the expanded RAM (XRAM), the EXTRAM bit must be set and MOVX instructions must be used. The expanded memory is physically located on the chip and logically occupies the first bytes of external memory (addresses 000H to 2FFH). When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3[6] (WR), P3[7] (RD), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. Expanded RAM access (indirect addressing only): MOVX @DPTR, A; DPTR contains 0A0H Table 5. AUXR - Auxiliary function register (address 8EH) bit allocation Not bit addressable; reset value 00H. Bit 7 6 5 4 3 2 1 0 Symbol - - - - - - EXTRAM AO |
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